Memory devices conventionally include arrays of bit cells that each store a bit of data. Each data bit can represent a logical zero (“0”) or a logical one (“1”), which may correspond to a state of the bit cell. During a read operation of a selected bit cell, a voltage level close to ground may be representative of “0” and a relatively higher voltage level may be representative of “1”. Bit lines are coupled to various bit cells in the memory array and the bit lines couple the bit cells to other components used in read/write operations.
Magnetoresistive random access memory (MRAM) is a non-volatile memory technology where data is stored based on magnetization polarities of bit cells. In contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements. A magnetic tunnel junction (MTJ) which is conventionally used as a storage element or bit cell for MRAM technology, can be formed from two magnetic layers, each of which can hold a magnetic moment, separated by an insulating (tunnel barrier) layer. Conventionally, the fixed layer is set to a particular polarity. The free layer's polarity is free to change to match that of an external magnetic field that can be applied. A change in the polarity of the free layer will change the resistance of the MTJ bit cell. For example, when the magnetization polarities are aligned or “parallel,” a low resistance state (RL) exists, which corresponds to a logical “0”. When the magnetization polarities are not aligned or are “anti-parallel,” a high resistance state (RH) exists, which corresponds to a logical “1”.
Thus, in magnetoresistive random access memory (MRAM), each bit cell (e.g., a MTJ bit cell) has a resistance value based on whether the bit cell represents a logical zero (“0”) or a logical one (“1”). Specifically, the resistance of the bit cell (Rdata) relates to the data stored in the bit cell.
Thus, in order to write a logical “0” or a logical “1,” corresponding write currents are passed through the MTJ bit cell to effect a corresponding alignment of the free layer and the fixed layer, or in other words to program the MTJ bit cell to the corresponding resistance state.
In order to read the bit cell, a sensing current is passed through the bit cell and a voltage Vdata developed across the resistance Rdata is then compared to a reference voltage Vref. If Vdata is high relative to Vref, then the bit cell is determined to have a logical “1” stored therein. If Vdata is low relative to Vref, then then the bit cell is determined to have a logical “0” stored therein. The difference between the voltage across the bit cell Vdata and the reference voltage Vref, (differential voltage ΔV=Vdata−Vref) is therefore used to indicate the logic state stored in the the bit cell. A sensing margin refers generally refers to the amount by which ΔV must be correctly sensed as positive or negative in order to correctly read the value stored in the bit cell as “1” or “0” respectively.
For the read operation, the sensing current needs to be less than the write currents used for writing the bit cell, in order to ensure that the data stored in the bit cell is not inadvertently flipped or reprogrammed during the read operation. If the read operation results in an undesired change in the logical value stored in the bit cell, this situation is referred to as a read disturbance.
A clamp transistor (e.g., a n-channel metal oxide semiconductor (NMOS) transistor) may be used to drive the sensing current through the bit cell. A gate voltage of the clamp transistor (or a clamp voltage VG_clamp) is adjusted or controlled in order to vary the amount of sensing current that is passed through the bit cell for a read operation. It may be desirable to maintain the clamp voltage VG_clamp to a low value in order to keep the sensing current low, with a view to avoiding read disturbance.
However, reducing the clamp voltage VG_clamp can lead to another undesirable effect which relates to a threshold voltage (Vth) of the clamp transistor. The threshold voltage of the clamp transistor is the minimum voltage that needs to be applied to the gate of the clamp transistor in order to activate the clamp transistor and cause it to drive the sensing current. If the clamp voltage VG_clamp is too low, then there is a risk that the clamp voltage VG_clamp may be lower than the threshold voltage Vth, which would prevent any sensing current from being driven to the bit cell. Further, the sensing current is also dependent on the difference between the clamp voltage VG_clamp and the threshold voltage Vth. However, the threshold voltage Vth can vary with process-voltage-temperature (PVT) conditions. Thus, the sensing current becomes heavily dependent on PVT variations, which makes the sensing operation unpredictable and unreliable.
Further, reducing the sensing current to a very low value can lead to a smaller sensing margin. A read access pass yield (RAPY) refers to a measure of a yield or percentage of read operations which result in a correct read value for a bit cell. Similarly, a read disturbance pass yield (RDPY) refers to a measure of yield or percentage of read operations which are not affected by read disturbance issues. For some PVT corners, for example, the variations in the sensing current may lead to an undesirably low sensing current, which can reduce the RAPY. At some other PVT corners, for example, the variation in sensing current can lead to an undesirably high sensing current which can result in a read disturbance.
Some conventional attempts to overcome the above problems with variation in sensing current include a bias generator which is configured to generate a clamp voltage VG_clamp and reference voltage Vref, by utilizing a current mirror and replica cells which are MTJ cells programmed to logical states “0” and “1” with corresponding resistances RL and RH. These bias generators require current to be flowing to these replica cells, which may in turn create another source for read disturbance. Moreover, since current needs to be generated from the current mirror to pass through the replica cells during read operations on the MRAM bit cells, additional power is consumed in the process. Thus, the bias generators are not an effective solution due to at least the above drawbacks.
Accordingly, there is continuing need in the art for reliable and constant sensing currents for MRAM read operations, where the sensing currents do not vary with PVT variations.